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| M7020R 32K x 68-bit Entry NETWORK SEARCH ENGINE DATA BRIEFING FEATURES SUMMARY s 32K DATA ENTRIES IN 68-BIT MODE s Figure 1. 272-ball PBGA Package s TABLE MAY BE PARTITIONED INTO UP TO FOUR (4) QUADRANTS (Data entry width in each octant is configurable as 34, 68, 136, or 272 bits.) UP TO 83 MILLION SUSTAINED SEARCHES PER SECOND IN 68-BIT and 136-BIT CONFIGURATIONS UP TO 41.5 MILLION SEARCHES PER SECOND IN 34-BIT and 272-BIT CONFIGURATIONS SEARCHES ANY SUB-FIELD IN A SINGLE CYCLE OFFERS BIT-BY-BIT and GLOBAL MASKING SYNCHRONOUS, PIPELINED OPERATION UP TO 31 SEARCH ENGINES CASCADABLE WITHOUT PERFORMANCE DEGRADATION WHEN CASCADED, THE DATABASE ENTRIES CAN SCALE FROM 248K TO 1984K DEPENDING ON THE WIDTH OF THE ENTRY GLUELESS INTERFACE TO INDUSTRYSTANDARD SRAMS SIMPLE HARDWARE INSTRUCTION INTERFACE IEEE 1149.1 TEST ACCESS PORT OPERATING SUPPLY VOLTAGES INCLUDE: VDD (Operating Supply Voltage) = 1.8V VDDQ (Operating Supply Voltage for I/O) = 2.5 or 3.3V 272 PBGA, 27mm x 27mm 272-ball PBGA 27mm x 27mm s s s s s s s s s s s December 2001 Complete data available on Data-on-Disc CD-ROM or at www.st.comComplete data available on Data-on-Disc CD-ROM or at www.st.com 1/6 M7020R DESCRIPTION Overview ST Microelectronics, Inc.'s M7020R Search Engine incorporates patent-pending Associative Processing TechnologyTM (APT) and is designed to be a high-performance, pipelined, synchronous, 32K-entry network database search engine. The M7020R database entry size can be 68 bits, 136 bits, or 272 bits. In the 68-bit entry mode, the size of the database is 32K entries. In the 136-bit mode, the size of the database is 16K entries, and in the 272-bit mode, the size of the database is 8K entries. The M7020R is configurable to support multiple databases with different entry sizes. The 34-bit entry table can be implemented using the Global Mask Registers (GMRs) building-database size of 64K entries with a single device. Performance The Search Engine can sustain 83 million transactions per second when the database is programmed or configured as 68 or 136 bits. When the database is programmed to have an entry size Table 1. Product Range Part Number M7020R-083ZA1 M7020R-066ZA1 M7020R-050ZA1 Operating Supply Voltage 1.8V 1.8V 1.8V Operating I/O Voltage 2.5 or 3.3V 2.5 or 3.3V 2.5 or 3.3V Speed 83MHz 66MHz 50MHz Temperature Range Commercial Commercial Commercial of 34 or 272 bits, the Search Engine will perform at 41.5 million transactions per second. STM's M7020R can be used to accelerate network protocols such as Longest-prefix Match (CIDR), ARP, MPLS, and other Layer 2, 3, and 4 protocols. Applications This high-speed, high-capacity Search Engine can be deployed in a variety of networking and communications applications. The performance and features of the M7020R make it attractive in applications such as Enterprise LAN switches and routers and broadband switching and/or routing equipment supporting multiple data rates at OC- 48 and beyond. The Search Engine is designed to be scalable in order to support network database sizes to 1984K entries specifically for environments that require large network policy databases. Figure 4, page 5 shows the block diagram for the M7020R device. Figure 2. Switch/Router Implementation Using the M7020R Sys tem Bus m Progra ry Memo Host ASIC Switch Fabric Ne two h Searc e Engin SRAM Bank rk L ine Inte Switch or rocess P rfac es AI04272 2/6 M7020R Table 2. Signal Names Symbol Type(1) Description LHI[6:0] LHO[1:0] BHI[2:0] BHO[2:0] FULI[6:0] FULO[1:0] FULL Cascade Interface I O I O I O O Local Hit In Local Hit Out Block Hit In Block Hit Out Full In Full Out Full Flag Clocks and Reset CLK2X PHS_L TEST RST_L I I I I Master Clock Phase Test Input Reset Command and DQ Bus CMD[8:0] CMDV DQ[67:0] ACK(4) EOT(4) SSF SSV I I I/O T T T T Command Bus Command Valid Address/Data Bus READ Acknowledge End of Transfer SEARCH Successful Flag SEARCH Successful Flag Valid Device Identification ID[4:0] I Device Identification Supplies VDD VDDQ n/a n/a Chip Core Supply (1.8V) Chip I/O Supply (2.5 or 3.3V) Test Access Port TDI TCK I I T I I Test Access Port's Test Data In Test Access Port's Test Clock Test Access Port's Test Data Out Test Access Port's Test Mode Select Test Access Port's Reset SRAM Interface SADR[21:0] CE_L WE_L OE_L ALE_L T T T T T SRAM Address SRAM Chip Enable SRAM Write Enable SRAM Output Enable Address Latch Enable TDO TMS TRST_L Note: 1. Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate 2. "CLK" is an internal clock signal. Any reference to "CLK Cycles" means one cycle of CLK. 3. ACK and EOT Signals require a weak, external pull-down resistor of 47 K or 100 K. 3/6 M7020R Figure 3. Connections NC NC DQ64 DQ62 GND NC NC NC EOT ACK NC VDD NC NC FULL NC NC VDD FULI5 FULI4 FULI1 BHO0 VDD FULO1 NC NC BHI0 LHI6 NC LHI3 VDD LHI2 ID2 ID0 TMS TCK TDO TDI NC NC VDD NC NC NC DQ65 FULI6 FULI2 BHO1 BHI2 VDDQ LHI5 NC VDDQ BHO2 VDD LHO1 ID3 ID1 VDDQ VDD VDDQ GND RSTL DQ66 LHI4 VDDQ LHI0 LHI1 ID4 NC FULO0 GND FULI3 FULI0 BHI1 LHO0 GND TOP T RST_L GND DQ63 DQ61 DQ57 NC DQ53 DQ60 VDDQ VDD NC DQ67 DQ59 DQ56 DQ58 VDDQ DQ55 DQ49 VDD DQ47 VDDQ DQ51 VDDQ GND GND GND GND GND GND GND GND GND RIGHT GND GND GND GND GND GND VDDQ NC NC DQ29 VDD NC DQ45 DQ43 DQ50 VDDQ DQ52 DQ54 NC DQ46 DQ48 GND DQ40 DQ42 VDDQ DQ44 VDD NC DQ36 DQ38 LEFT VDDQ DQ34 DQ32 DQ30 NC DQ28 VDDQ DQ26 DQ20 GND DQ41 DQ39 VDD DQ37 VDDQ DQ35 DQ33 DQ31 GND GND DQ23 DQ25 DQ27 DQ24 VDD GND DQ19 VDDQ DQ21 VDDQ NC DQ15 DQ17 DQ22 DQ16 DQ14 VDDQ VDD DQ18 VDDQ DQ6 NC DQ10 DQ2 NC NC DQ12 DQ8 NC DQ4 NC NC DQ0 NC BOTTOM DQ9 DQ11 DQ13 VDD DQ1 DQ5 NC DQ7 NC NC VDDQ DQ3 NC NC VDDQ GND VDD NC SADR SADR V GND VDDQ CMD4 CMD2 GND WE_L CLK2X VDD DDQ GND 15 5 SADR SADR SADR SADR SADR SADR SADR NC 21 18 6 16 9 7 12 SADR V DDQ 19 NC SADR SADR NC 10 11 SSF CMD6 CMD3 CMD0 AE_L OE_L SADR V DD 0 NC SSV CMD5 CMD1 CMDV VDDQ PHS_L VDDQ NC CE_L NC SADR SADR 4 3 CMD8 CMD7 VDDQ VDD VDD SADR SADR SADR SADR VDD SADR VDDQ SADR SADR 2 1 20 14 8 17 13 AI04270 4/6 M7020R Figure 4. M7020R Block Diagram PHS_L CLK2X RST_L Comparand Registers[15:0] Global Mask Registers [7:0] Information and Command Register Burst Read Register Burst Write Register Next Free Address Register Search Successful Index Registers [7:0] (All registers are 68-bit-wide) TAP Controller TAP DQ [67:0] Compare/PIO Data Cmd Compare/PIO Data Address Decode CMD [8:0] CMDV ACK EOT Priority Encode Match Logic Command Decode and PIO Access Configurable as 64K x 34 32K x 68 16K x 136 8K x 272 Data Array Configurable as 64K x 34 32K x 68 16K x 136 8K x 272 Mask Array SADR [21:0] Pipeline and SRAM Control OE_L WE_L CE_L ALE_L ID [4:0] FULL [6:0] Full Logic FULL LHI [6:0] BHI [2:0] Arbitration Logic FULO [1:0] LHO [1:0] BHO [2:0] SSF SSV AI04271 5/6 M7020R PART NUMBERING Table 3. Ordering Information Scheme Example: M70 20 R -083 ZA 1 T Device Type M70 Search Engine Density 20 = 2Mb (32K x 68-bit Table Entries) Operating Supply Voltage R = VDD = 1.8V Speed -083 = 83 Million Searches per Second -066 = 66 Million Searches per Second -050 = 50 Million Searches per Second Package PBGA = 272-ball count, 27mm x 27mm(1), 1.27mm ball pitch Temperature Range 1 = 0 to 70C Shipping Option Tape & Reel Packing = T Note: 1. Where "Z" is the symbol for BGA packages and "A" denotes 1.27mm ball pitch For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 6/6 |
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